The “background” description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly or impliedly admitted as prior art against the present invention.
Complimentary metal-oxide-semiconductor (CMOS) to current mode logic (CML) interfaces are common. For example, CMOS to CML interfaces can be used in digital-to-analog converters (DAC), decision feedback equalizers (DFE), and the like. The CMOS domain of the interface offers low power, but has limited speed. Accordingly, at some point in the circuit, structure switches from the low power CMOS domain to the faster CML domain of the interface in order to accommodate higher speed switching requirements. However, the faster switching speeds of the CML domain comes at the expense of greater power consumption. Therefore, improvements to the CMOS to CML interfaces are desired to increase performance while minimizing increases in power consumption.